This invention relates generally to techniques for packaging circuit elements and, more particularly, to techniques for packaging integrated-circuit (IC) chips.
Conventional packaging techniques utilize ceramic chip packages, multilayer circuit boards and "mother" boards to interconnect large numbers of integrated-circuit chips. The IC chips are generally connected to one of the multilayer printed circuit boards by first mounting and interconnecting the IC chip with a ceramic chip package. This first interconnect is commonly referred to as a Level 1 interconnect. The ceramic chip package is then connected to the multilayer circuit board, known as a Level 2 interconnect. The multilayer printed circuit board is interconnected with other multilayer printed circuit boards by means of the "mother" board, which has connectors into which the circuit boards are plugged. Alternatively, cable harnesses can be utilized to interconnect the multiple printed circuit boards. This final interconnect is commonly referred to as a Level 3 interconnect.
An integrated-circuit chip generally includes thousands of microscopic circuit elements, such as transistors, resistors and capacitors, arranged in various circuit configurations. The circuit elements are interconnected within the IC chip, with the input/output leads of the various circuits connected to conductive areas or pads located around the periphery of the IC chip. A conventional technique for effecting a Level 1 interconnect includes connecting the conductive pads to pins located around the periphery of the ceramic chip package by soldering extremely fine wires between the chip pads and the chip package pins.
This conventional technique for effecting a Level 1 interconnect has many disadvantages. One of the disadvantages is that soldering fine wires between the chip pads and the chip package pins requires expensive tooling and special labor, which is typically available only at a factory. In addition, each interconnection between a chip pad and the multilayer printed circuit board requires four connections, including the two ends of each wire and the two ends of each chip package pin, severely limiting the quality of the connection. Another disadvantage is that the fine wire causes an increase in the interconnect inductance.
The conventional techniques for effecting a Level 2 interconnect utilize various types of IC chip packages, such as dual-in-line (DIP) packages, pin grid arrays and leadless chip packages. A dual-in-line package has pins positioned around the periphery of the chip package that plug into matching receptacles on the multilayer printed circuit board. One problem with this approach is that, because of the large number of input/output leads required by conventional IC chips and the spacing required between the pins, the chip package has an area three to four times the area of the IC chip. This not only limits the number of chips that can be placed on a multilayer printed circuit board, but also increases the distance between the IC chips, significantly increasing signal propagation time. A pin grid array, a chip package having an array of pins extending from the bottom of the chip package, was developed to increase the number of input/output leads without an increase in the chip package size. However, the large number of through holes required in the multilayer printed circuit board to effect the interconnection reduces the interwiring capability of the buried layers, thus requiring a substantial increase in the number of layers. A leadless chip package has contact bumps which are soldered to contact pads on the multilayer printed circuit board. However, the thermal expansion differential between the chip package and the circuit board often shears the solder joints.
The IC chip packages and multilayer printed circuit boards used in conventional packaging techniques present some further problems. One is that the use of a chip package increases the overall capacitance of the system, thus limiting operation of the system at high speeds. Another problem is that the chip package inhibits heat transfer between the IC chip and a heat sink, thus raising the operating temperature of the chip. One problem with using multilayer printed circuit boards is that conventional high speed circuit designs require up to two hundred input/output leads, and future designs could easily extend this requirement to about five hundred leads. Accommodating a modest chip package having 132 leads requires a multilayer printed circuit board with over sixteen layers. Some multilayer circuit boards are presently being manufactured with over thirty-three layers. Circuit boards of this complexity require considerable time to design and manufacture, and a design change of even the simplest nature can result in discarding the whole board.
Another problem with using multilayer printed circuit boards is that they are usually constructed of materials such as epoxy glass, Polymide, or a ceramic material, such as aluminum oxide (Al.sub.2 O.sub.3). All of these materials have a relatively high dielectric constant, which increases the distributed capacitance of the interconnections to the point that the capacitance can become so high as to require a charging current that is a significant percentage of the total dissipated in the circuitry. Therefore, the distributed capacitance of the interconnections effectively limits the length of the interconnections, if the capacitance values are to be kept within reasonable limits. For typical high speed systems, the circuit boards may have geometric features with widths of approximately 0.007 inches, and spacings with the same dimension. For these geometric values, the distributed capacitance limits the maximum lead length to about 10 to 15 inches. Another and even more important problem caused by the use of these multilayer circuit board materials is the long signal propagation time resulting from the high interconnection reactances, which may render a high speed system completely inoperative or, at the very best, extremely limited in operating speed and data throughput.
The conventional techniques for effecting a Level 3 interconnect, "mother" boards and cable harnesses, also have many disadvantages. One disadvantage of interconnecting the circuit boards with cable harnesses is that the interconnecting cables contribute a large amount of capacitance and inductance, thus limiting operation of the system at high speeds. Insulation material used in the cable harnesses further increases interconnection reactances, thus aggravating the problem. Moreover, the use of cable harnesses can add as much as twenty-five percent to the volume of the system, and can add accordingly to the weight. Another disadvantage is that mother boards and cable harnesses add considerably to the cost of the system. A further disadvantage is that all input and output leads in each multilayer printed circuit board must terminate at an edge of the board, for attachment to one of the back-panel connectors. Therefore, a signal originating at an area of the board remote from the edge connector must weave its way through other conductors and circuit elements on the board. This necessitates long lead lengths and complicates the board design, often requiring unnecessary board layers and a higher density of wiring.
To obviate or minimize the disadvantages and problems arising from the use of conventional interconnection techniques, it has become apparent that a new packaging approach must be employed. The new approach should preferably eliminate the need for many of the conventional interconnection techniques. The new approach should also minimize the lead lengths between interconnected circuits, and provide a correspondingly high packing density that makes more effective use of modern integrated-circuit fabrication techniques. The present invention is directed to these ends.